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TMS320C5515
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
Table 2-18. GPIO Terminal Functions (continued)
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SIGNAL
NAME
LCD_D8]/
I2S2_CLK/
GP[18]/
SPI_CLK
LCD_D[9]/
I2S2_FS/
GP[19]/
SPI_CS0
LCD_D[10]/
I2S2_RX/
GP[20]/
SPI_RX
NO.
N10
P11
N11
TYPE (1)
(2)
I/O/Z
I/O/Z
I/O/Z
OTHER (3)
IPD
DV DDIO
BH
IPD
DV DDIO
BH
IPD
DV DDIO
BH
(4)
DESCRIPTION
This pin is multiplexed between LCD Bridge and GPIO.
For GPIO, it is general-purpose input/output pin 18 (GP[18]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, I2S2, and GPIO.
For GPIO, it is general-purpose input/output pin 19 (GP[19]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, I2S2, GPIO and SPI.
For GPIO, it is general-purpose input/output pin 20 (GP[20]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between EMIF and GPIO.
IPD
For GPIO, it is general-purpose input/output pin 21 (GP[21]).
EM_A[15]/GP[21]
N1
I/O/Z
DV DDEMIF
BH
Mux control via the A15_MODE bit in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
This pin is multiplexed between EMIF and GPIO.
IPD
For GPIO, it is general-purpose input/output pin 22 (GP[22]).
EM_A[16]/GP[22]
E2
I/O/Z
DV DDEMIF
BH
Mux control via the A16_MODE bit in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
This pin is multiplexed between EMIF and GPIO.
IPD
For GPIO, it is general-purpose input/output pin 23 (GP[23]).
EM_A[17]/GP[23]
F2
I/O/Z
DV DDEMIF
BH
Mux control via the A17_MODE bit in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
This pin is multiplexed between EMIF and GPIO.
IPD
For GPIO, it is general-purpose input/output pin 24 (GP[24]).
EM_A[18]/GP[24]
G2
I/O/Z
DV DDEMIF
BH
Mux control via the A18_MODE bit in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
This pin is multiplexed between EMIF and GPIO.
IPD
For GPIO, it is general-purpose input/output pin 25 (GP[25]).
EM_A[19]/GP[25]
G4
I/O/Z
DV DDEMIF
BH
Mux control via the A19_MODE bit in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
This pin is multiplexed between EMIF and GPIO.
IPD
For GPIO, it is general-purpose input/output pin 26 (GP[26]).
EM_A[20]/GP[26]
J3
I/O/Z
DV DDEMIF
BH
Mux control via the A20_MODE bit in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
LCD_D[11]/
I2S2_DX/
GP[27]/
SPI_TX
LCD_D[12]/
UART_RTS/
GP[28]/
I2S3_CLK
P12
N12
I/O/Z
I/O/Z
IPD
DV DDIO
BH
IPD
DV DDIO
BH
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
For GPIO, it is general-purpose input/output pin 27 (GP[27]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
For GPIO, it is general-purpose input/output pin 28 (GP[28]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
40
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